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ORCIDChao Fang 0005
Person information
- affiliation: Shanghai Qi Zhi Institute, Shanghai, China
- affiliation (PhD 2025): Nanjing University, School of Electronic Science and Engineering, Nanjing, China
Other persons with the same name
- Chao Fang — disambiguation page
- Chao Fang 0001
![[0000-0002-7611-4077]](https://google.otrosproyectosundfe.com/https://dblp.org/img/orcid-mark.12x12.png "0000-0002-7611-4077")
— Beijing University of Technology, Beijing Advanced Innovation Center for Future Internet Technology, China (and 1 more) - Chao Fang 0002 — Chalmers University of Technology, Department of Signals and Systems, Gothenburg, Sweden
- Chao Fang 0003 — Xidian University, National Key Laboratory of Radar Signal Processing, Xi'an, China
- Chao Fang 0004 — Chinese Academy of Sciences, Changchun Institute of Optics, Fine Mechanics and Physics, China
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2020 – today
- 2026
[j6]Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang:
APT-LLM: Exploiting Arbitrary-Precision Tensor Core Computing for LLM Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 45(4): 1935-1948 (2026)- [c18]Stef Cuyckens, Xiaoling Yi, Robin Geens, Joren Dumoulin, Martin Wiesner, Chao Fang, Marian Verhelst:
Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration. ASP-DAC 2026: 611-617 - [c17]Jun Yin, Chao Fang, Ryan Antonio, Xiaoling Yi, Yunhao Deng, Fanchen Kong, Marian Verhelst:
STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications. CICC 2026: 1-4 - 2025
- [j5]Mingkai Tang, Ren Xin, Chao Fang, Yuanhang Li, Hongji Liu, Jin Wu:
GPU-accelerated Conflict-based Search for Multi-agent Embodied Intelligence. Mach. Intell. Res. 22(4): 641-654 (2025) - [j4]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 207-220 (2025) - [c16]Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang:
Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores. ASP-DAC 2025: 1181-1187 - [c15]Chao Fang, Man Shi, Robin Geens, Arne Symons, Zhongfeng Wang, Marian Verhelst:
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format. HPCA 2025: 1467-1481 - [c14]Stef Cuyckens, Xiaoling Yi, Nitish Satya Murthy, Chao Fang, Marian Verhelst:
Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning. ISLPED 2025: 1-7 - [c13]Stef Cuyckens, Ryan Antonio, Chao Fang, Marian Verhelst:
iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator. PRIME 2025: 1-4 - [i19]Zhibin Wang, Rui Ning, Chao Fang, Zhonghui Zhang, Xi Lin, Shaobo Ma, Mo Zhou, Xue Li, Zhongfeng Wang, Chengying Huan, Rong Gu, Kun Yang, Guihai Chen, Sheng Zhong, Chen Tian:
FlashForge: Ultra-Efficient Prefix-Aware Attention for LLM Decoding. CoRR abs/2505.17694 (2025) - [i18]Qiong Li, Chao Fang, Longwei Huang, Jun Lin, Zhongfeng Wang:
Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing. CoRR abs/2505.19096 (2025) - [i17]Stef Cuyckens, Xiaoling Yi, Nitish Satya Murthy, Chao Fang, Marian Verhelst:
Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning. CoRR abs/2505.22404 (2025) - [i16]Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang:
APT-LLM: Exploiting Arbitrary-Precision Tensor Core Computing for LLM Acceleration. CoRR abs/2508.19087 (2025) - [i15]Stef Cuyckens, Ryan Antonio, Chao Fang, Marian Verhelst:
iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator. CoRR abs/2511.05503 (2025) - [i14]Stef Cuyckens, Xiaoling Yi, Robin Geens, Joren Dumoulin, Martin Wiesner, Chao Fang, Marian Verhelst:
Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration. CoRR abs/2511.06313 (2025) - [i13]Yuzong Chen, Chao Fang, Xilai Dai, Yuheng Wu, Thierry Tambe, Marian Verhelst, Mohamed S. Abdelfattah:
P3-LLM: An Integrated NPU-PIM Accelerator for LLM Inference Using Hybrid Numerical Formats. CoRR abs/2511.06838 (2025) - 2024
- [j3]Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang:
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 506-519 (2024) - [c12]Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. ASPDAC 2024: 927-932 - [c11]Yuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang:
Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment. ICCAD 2024: 180:1-180:9 - [c10]Yuhao Ji, Chao Fang, Zhongfeng Wang:
BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge. ISCAS 2024: 1-5 - [c9]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. ISCAS 2024: 1-5 - [c8]Robin Geens, Man Shi, Arne Symons, Chao Fang, Marian Verhelst:
Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators. SOCC 2024: 1-6 - [i12]Yuhao Ji, Chao Fang, Zhongfeng Wang:
BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge. CoRR abs/2401.11851 (2024) - [i11]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR abs/2401.16872 (2024) - [i10]Yuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang:
Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment. CoRR abs/2407.12070 (2024) - [i9]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR abs/2409.14017 (2024) - [i8]Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang:
Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores. CoRR abs/2409.17870 (2024) - [i7]Chao Fang, Man Shi, Robin Geens, Arne Symons, Zhongfeng Wang, Marian Verhelst:
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format. CoRR abs/2411.15982 (2024) - 2023
- [c7]Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang:
CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks. DATE 2023: 1-2 - [c6]Jiayi Tian, Chao Fang, Haonan Wang, Zhongfeng Wang:
Bebert: Efficient And Robust Binary Ensemble Bert. ICASSP 2023: 1-5 - [c5]Qiong Li, Chao Fang, Zhongfeng Wang:
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications. ISCAS 2023: 1-5 - [i6]Qiong Li, Chao Fang, Zhongfeng Wang:
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications. CoRR abs/2302.01876 (2023) - [i5]Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. CoRR abs/2309.08186 (2023) - [i4]Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang:
Efficient N: M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. CoRR abs/2309.13015 (2023) - 2022
- [j2]Chao Fang, Aojun Zhou, Zhongfeng Wang:
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1573-1586 (2022) - [c4]Chao Fang, Shouliang Guo, Wei Wu, Jun Lin, Zhongfeng Wang, Ming Kai Hsu, Lingzhi Liu:
An Efficient Hardware Accelerator for Sparse Transformer Neural Networks. ISCAS 2022: 2670-2674 - [i3]Chao Fang, Aojun Zhou, Zhongfeng Wang:
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. CoRR abs/2208.06118 (2022) - [i2]Jiayi Tian, Chao Fang, Haonan Wang, Zhongfeng Wang:
BEBERT: Efficient and robust binary ensemble BERT. CoRR abs/2210.15976 (2022) - 2021
- [j1]Jinming Lu, Chao Fang, Mingyang Xu, Jun Lin, Zhongfeng Wang:
Evaluations on Deep Neural Networks Training Using Posit Number System. IEEE Trans. Computers 70(2): 174-187 (2021) - [c3]Chao Fang, Liulu He, Haonan Wang, Jinghe Wei, Zhongfeng Wang:
Accelerating 3D Convolutional Neural Networks Using 3D Fast Fourier Transform. ISCAS 2021: 1-5 - 2020
- [c2]Shouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang:
A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. SoCC 2020: 174-179
2010 – 2019
- 2019
- [c1]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. SoCC 2019: 62-67 - [i1]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. CoRR abs/1909.03831 (2019)
Coauthor Index
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