Question Zen 6 Speculation Thread

[StefanR5R]

Are they copying the P+E style approach from Intel so it's similar to an E core, or is it similar to the LPE cores that Intel is using for NVL, or is AMD just re-using existing Zen Classic or Zen Dense cores but running them at lower frequency meaning lower power, or something else?

Intel's approach:
They have two internally competing microarchitectures. In server, they release CPUs with either the fat µarch or the slim µarch. In client, they threw both µarches in, and eventually they went further by providing cores of the slim µarch configured for different f_max and differently placed in the SoC topology. The mentioned two competing µarches happen to have different native ISAs. Intel "solved" the problems which arose from mixing µarches which differed this way by dumbing down the ISA support of their fatter µarch. Going forward, the slimmer µarch is of course supposed to gain some more ISA capability, eventually.

AMD's approach:
So far they make products with a single microarchitecture (per Zen generation), but with different physical core designs (classic, dense) and different SoC makeups (WRT topology and WRT last level cache size). In Zen 5, they also started to split the FPU/ vector pipeline into two different designs: A wide one used in server and some client products, and a narrower double pumped one used in the rest of the client products. Starting with Zen 6, another core variant will appear, the low power cores, which are rumored to be a further cut down µarch. However, it is safe to assume that this extra µarch will be fully compatible with the ISA of AMD's main µarch which is used in the various classic<->dense and server<->client products. IOW AMD will presumably equip the small µarch with all of the ISA smarts, instead of dumbing their main µarch down.

 

[511]

They have two internally competing microarchitectures. In server, they release CPUs with either the fat µarch or the slim µarch. In client, they threw both µarches in, and eventually they went further by providing cores of the slim µarch configured for different f_max and differently placed in the SoC topology. The mentioned two competing µarches happen to have different native ISAs. Intel "solved" the problems which arose from mixing µarches which differed this way by dumbing down the ISA support of their fatter µarch. Going forward, the slimmer µarch is of course supposed to gain some more ISA capability, eventually.

Well Intel's Atom was intended for Mobile Phones not E cores in desktop also Intel is now taking a page out of AMD's book since now it's expensive for them to maintain two design without significant ROI.

 

[Fjodor2001]

Intel's approach:
They have two internally competing microarchitectures. In server, they release CPUs with either the fat µarch or the slim µarch. In client, they threw both µarches in, and eventually they went further by providing cores of the slim µarch configured for different f_max and differently placed in the SoC topology. The mentioned two competing µarches happen to have different native ISAs. Intel "solved" the problems which arose from mixing µarches which differed this way by dumbing down the ISA support of their fatter µarch. Going forward, the slimmer µarch is of course supposed to gain some more ISA capability, eventually.

Yeah, the idea with P+E cores is the big.LITTLE approach used by basically all major companies producing CPUs for client (except AMD). Idea is that for most workloads you usually only need a certain number of big cores running at max ST perf, and the rest of the work is MT which is more efficiently handled by LITTLE cores.

W.r.t. ISA, not sure in what way you mean different ISA is used for P vs E cores on NVL. To my understanding they are both compatible with the same ISA. Also, not sure why you mean Intel dumbed down the big (P) cores on NVL.

Also, not sure what the relationship your comment has to the Intel LP-E cores. To my understanding the LP-E core type is also ISA compliant with the P and E cores on NVL.

Starting with Zen 6, another core variant will appear, the low power cores, which are rumored to be a further cut down µarch. However, it is safe to assume that this extra µarch will be fully compatible with the ISA of AMD's main µarch which is used in the various classic<->dense and server<->client products. IOW AMD will presumably equip the small µarch with all of the ISA smarts, instead of dumbing their main µarch down.

Yes, from the Twitter I posted recently in this thread, Zen6 LP-E will be a hybrid of Zen5 with Zen6 ISA. Sounds like similar approach to what Intel is taking with their LP-E cores, which are also ISA compliant with the P and E cores on NVL, but less fat than those two cores types. So AMD Zen6 will use same ISA on Classic, Dense, and LP-E. Same as Intel which is using same ISA for P, E, and LP-E.

 

[adroc_thurston]

Sounds like similar approach to what Intel is taking with their LP-E cores, which are also ISA compliant with the P and E cores on NVL, but less fat than those two cores types.

Intel atoms are the same.
This is a different core altogether.

 

[Geddagod]

Yeah, the idea with P+E cores is the big.LITTLE approach used by basically all major companies producing CPUs for client (except AMD). Idea is that for most workloads you usually only need a certain number of big cores running at max ST perf, and the rest of the work is MT which is more efficiently handled by LITTLE cores.

Apple recently changed, but Qcomm also goes with the P-core majority approach in their laptop high core count skus.
Little cores mostly seems to be for the area savings, not because the -M cores are inherently more power efficient at the boost clocks that these chips run at for nT, even in smartphones. The difference is at best seems to be negligible, if even non-existent (for power).

W.r.t. ISA, not sure in what way you mean different ISA is used for P vs E cores on NVL. To my understanding they are both compatible with the same ISA. Also, not sure why you mean Intel dumbed down the big (P) cores on NVL.

He didn't even mention NVL, except for the very last line, where he said going forward the E-cores will be beefed up so that the P and E cores, and thus the entire SOC, can finally support AVX-512.

 

[Fjodor2001]

Intel atoms are the same.
This is a different core altogether.

You mean Intel E and LP-E cores are exactly the same core (but that the latter is clocked lower), however AMD LP-E is a different core than Classic and Dense (this is already known from recent Tweet in this thread)?

 

[Fjodor2001]

Apple recently changed, but Qcomm also goes with the P-core majority approach in their laptop high core count skus.
Little cores mostly seems to be for the area savings, not because the -M cores are inherently more power efficient at the boost clocks that these chips run at for nT, even in smartphones. The difference is at best seems to be negligible, if even non-existent (for power).

Not sure what you mean that Apple changed. They are still using big.LITTLE style on client (desktop, laptop, and mobile such as iPad/iPhone).

If you claim little cores do not have better perf/watt than BIG cores within their respective operating range, I think you need to show some evidence to back that up.

Also, even if they would have the same perf/watt, area savings is still a win. Means better perf/$.

He didn't even mention NVL, except for the very last line, where he said going forward the E-cores will be beefed up so that the P and E cores, and thus the entire SOC, can finally support AVX-512.

Well, we're talking about Zen6 meaning next gen, so implicitly it means NVL for corresponding Intel unless otherwise mentioned. Sound like he missed mentioning he was comparing current gen Intel with next gen AMD.

 

[adroc_thurston]

You mean Intel E and LP-E cores are exactly the same core (but that the latter is clocked lower), however AMD LP-E is a different core than Classic and Dense (this is already known from recent Tweet in this thread)?

Yeah

 

[Geddagod]

Not sure what you mean that Apple changed. They are still using big.LITTLE style on client (desktop, laptop, and mobile such as iPad/iPhone).

Apple changed when they introduced "-S" and "-P" cores with the M5. The current M5 Max is 6 super cores + 12 performance cores, while the M4 max was 12 "-S" cores (by the new nomenclature) with 4-ecores.
As you see, previously Apple used -E cores as a LP island. Currently, Apple is using the "little" part of big.little as nT scalers.
Unlike what you said before, there's actually 2 ways companies use big.little (and sometimes companies do both).
One, as nT scaling for better perf/area (M5 max), as you alluded to originally. The other way is an LP island to help improve idle and low intensity workload power (M4 max).

If you claim little cores do not have better perf/watt than BIG cores within their respective operating range, I think you need to show some evidence to back that up.

Look at any modern mobile core's perf/watt curves from Geekerwan. Here's the mediatek 9500 for example.

For the vast, vast majority of the C1 Premium's curve, it gets outclassed by the C1 Ultra in perf/watt. Only the smallest E-cores have any reasonable reason to exist for perf/watt savings, and that's not even for perf/watt, just esentially Vmin. You cans see with this core even, that the half way across even the smallest core's perf/watt curve, the P-core overtaking it.
Similar story with Qcomm:


The E-cores in laptops, and the M-cores in smartphones, just look like perf/mm2-maxers. There is no meaningful perf/watt benefit.

We're talking about Zen6 meaning next gen, so implicitly it means NVL for corresponding Intel unless otherwise mentioned. Sound like he missed mentioning he was comparing current gen Intel with next gen AMD.

He wasn't even comparing current gen Intel with AMD's next gen. Did you even bother reading his comment?
He compared the past, present and future Intel's strategy... with the same past, present, and future of AMD.

 

[Fjodor2001]

Yeah

Ok, interesting. Potentially it opens up for better perf/watt on Zen6 LP-E compared to NVL LP-E, assuming the former is prioritizing perf/watt over perf/area.

But we'll have to see if that is the case, and how much the difference is in practice.

 

[Covfefe]

Well you only showed a Mediatek case. What about the below then:

I know it's from Intel (and not next gen) so it cannot be fully trusted since kinda marketing, but still.


Even if it would be the same perf/watt it's still a win if it has better perf/$, right? I mean consumers have limited $ to spend, so better perf/$ is good.
(I know this is kinda goal post shifting, but still. 😉 )

That chart is comparing p cores against lpe cores. The better efficiency in this case is due to uncore.

 

[Fjodor2001]

That chart is comparing p cores against lpe cores. The better efficiency in this case is due to uncore.

Well, Intel E core and LP-E cores should be the same according to adroc. The graph does not mention that the perf/watt difference should be due to uncore (only).

Anyway, I'm pretty sure I've seen E vs P core & big vs LITTLE core graphs showing better perf/watt within their respective operating ranges (for Apple, ARM, and Intel CPUs, where the source of the info is not the CPU vendor). But I'm busy watching the World Cup now so have limited time digging for evidence. Sorry for that. 🙂

 

[Covfefe]

Well, Intel E core and LP-E cores should be the same according to adroc. The graph does not mention that the perf/watt difference should be due to uncore (only).

Anyway, I'm pretty sure I've seen E vs P core & big vs LITTLE core graphs showing better perf/watt within their respective operating ranges (for Apple, ARM, and Intel CPUs, where the source of the info is not the CPU vendor). But I'm busy watching the World Cup now so have limited time digging for evidence. Sorry for that. 🙂

The microarchitecture and physical layout of the core is the same. The uncore is different.

If you're trying to determine the efficiency of the core microarchitecture, lpe cores aren't a fair comparison.

 

[poke01]

Well Intel's Atom was intended for Mobile Phones

LOL i can't. they thought those Atom cores are good for phones....... skymont/darkmont still isn't good for phones. weak perf/w